This invention relates to the field testing of electronic assemblies within customer products, and more particularly, to built-in self-test methodologies for testing electronic components within peripheral devices such as printers.
There presently exist techniques for testing electronic assemblies using relatively expensive external test equipment. Over the years, integrated circuits (ICs) have become an important part of many devices and electronic assemblies. It is desirable to identify defective interconnections, circuit pathways and junctions in a circuit device by testing circuit devices in order to identify such problems. A number of techniques have been developed to test such circuit devices.
One such technique employs the use of built-in self-test (BIST) circuitry which can be fabricated directly onto circuit devices such as integrated circuits. Built-in self-test (BIST) comprises signature analysis that provides a design-for-testability technique. However, additional logic in the form of linear feedback shift registers is needed to automatically generate pseudo-random test vectors. Output responses are compressed to form single vectors that are compared to a known good vector. When the output response vector does not match the known good vector, the design is considered faulty. However, a relatively large number of pseudo-random test vectors need to be exercised in order to ensure that an acceptably small chance of false positive results is realized.
Another technique for testing circuit components is called boundary scan. Boundary scan provides a technique for testing electronic assemblies. For example, a piece of test equipment can be connected to an electronic assembly such that verification can be made to show that all the digital components are in place, connected, and functioning properly. Boundary scan has been defined for testing integrated circuits (ICs) on printed circuit boards. Boundary scan imposes design discipline on printed circuit board components, including integrated circuits (ICs). Input/Output (I/O) pins on the integrated circuits can be connected into scan chains, with each integrated circuit containing scan registers between the I/O pins and a core logic which enables the printed circuit board test bus to control and observe the behavior of individual integrated circuits.
Further details of boundary scan testing can be found in U.S. Pat. Nos. 5,497,378 and 5,691,991 issued to International Business Machines Corporation, and various papers referenced therein. One accepted standard is described and fully documented in IEEE/ANSI Standard 1149.1-1990 Test Access Port and Boundary-Scan Architecture, herein incorporated by reference as illustrating the present understanding in the art. However, existing methods of boundary scan require expensive, special purpose equipment and software. For example, a typical implementation requires a relatively high investment in the range of $10,000-$200,000 (USD), which limits the number of applications where such implementation is cost-effective and/or feasible.
Therefore, there exists a need for an improved apparatus and method for testing electronic assemblies via boundary scan techniques wherein the need for special purpose equipment is eliminated and the implementation cost is reduced.
A technique is disclosed for performing boundary scan on devices that have an interface port, such as a parallel port connector, following the signaling scheme provided in IEEE Standard 1284. Such technique comprises an apparatus and a method for testing electronic assemblies that uses software on a host computer to control a circuit board of the electronic assembly in order to implement a boundary scan operation.
According to one aspect, a digital component test apparatus is provided. The apparatus includes a network environment, a client computer, a server computer, a device and an application program. The client computer is operatively connected with the network environment. The server computer is operatively connected with the network environment. The device has an electronic assembly and an interface port. The interface port is configured to connect the client computer with the electronic assembly. The application program is transferred from the network server to the client computer via the network. The application program includes a boundary scan test procedure operative to test operation of the electronic assembly.
According to another aspect, an apparatus is provided for testing electronic assemblies. The apparatus includes a networked computer system, an electronic assembly, and an application program. The networked computer system includes a network, a client computer operatively connected with the network, and a server computer operatively connected with the network. The electronic assembly includes an interface port and an application specific integrated circuit (ASIC). The interface port is configured to connect the client computer with the electronic assembly. The application program is transferred from the network server to the client computer via the network. The application program includes a boundary scan test procedure operative to test operation of the electronic assembly.
According to yet another aspect, a method is provided for remotely testing a peripheral device having an electronic assembly. The method includes the steps of: accessing a network remote site associated with the peripheral device with a host computer; downloading a control program configured to control the electronic assembly and perform a boundary scan operation on the electronic assembly onto the host computer; connecting the host computer with the electronic assembly of the peripheral device via an interface port; and performing a boundary scan operation on the electronic assembly remotely with the host computer.
One advantage of the invention comprises the ability to remotely test electronics within an electronic assembly of a device. Another advantage of the invention is provided by the ability to implement remote testing at a reduced cost.